Hybrid MEMS

• Accurate conductor shapes and alignment (impedance +/-4%).

• > 3X design density allotment than MLC/MLO/HDI; 20-50% less total # of layers.

SI / PI

• Vertical Via Shield***

• Conductor density, shape, roughness control.

• Dielectric thickness control ***

• C4 pad shield***

Build-Up

• Flexible Dielectric thickness control ***

• Layer level quality verification and electrical test***- 0 defect control process & High Yield.

• C4 side alignment control +/-2µm ***

• Flatness <µm.

• Larger C4 pads than MLC/MLO/HDI; 5-15µm pad to pad clearance.

Curing

• Low Dielectric loss.

• Low leakage.

• Low-High temperature CTE control;  CTE on C4 side 5-7 ppm.

• Consistent Dielectric properties thru-out the interface.

Plating

• Electrolytic plating only to maintain the consistent & optimal conductor properties.

• Lowest roughness / Reduced Skin Effect.

• Consistent signal propagation.

• Better Power / CCC control.

Base Carrier                                                            

• High flexural strength.                           

• Support >200Kg of Probe Force.              

• Low warpage/flatness overtime.

Simpler Fabrication processes

AVIV Hybrid MEMS Process ~ less 15 processes (very low chemical waste).